Fault tolerance in a systolic residue arithmetic processor array
Journal Article
·
· IEEE Trans. Comput.; (United States)
The technique described in this paper exploits the regularity of systolic arrays and the potential for redundancy in residue number systems to provide fault tolerance in VLSI systems. The fault tolerance is concurrent with normal circuit operations and allows a continuous flow of correct data when a fault occurs. There is no interruption of valid data flow while the circuits are reconfigured. The technique also obviates the need for ultrahigh-reliability switches and switching control circuits. A fault-tolerant implementation of a finite impulse response filter with five residue channels, two of which are redundant, demonstrate the technique. As long as not more than one cell in each processing block is faulty, the filter outputs contain no errors.
- Research Organization:
- The Mitre Corp., Bedford, MA (US)
- OSTI ID:
- 6992967
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:7; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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