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On mapping algorithms to linear and fault-tolerant systolic arrays

Journal Article · · IEEE Trans. Comput.; (United States)
DOI:https://doi.org/10.1109/12.21135· OSTI ID:6243175

The authors develop a simple mapping technique to design systolic arrays with limited I/O capability. Using this, improved systolic algorithms are derived for some matrix computations, on linearly connected arrays of processing elements (PEs) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data input/ouput format, and improved delay time. They extend the technique to design an optimal time systolic algorithm for n x n matrix multiplication. In this model, the propagation delay is assumed to be proportional to wire length. Fault reconfiguration is achieved by using buffers to bypass faulty PE's, which does not affect the clock rate of the system. The unidirectional flow of control and data in our design assures correctness of the algorithm in the presence of faulty PE's. This design can be implemented on reconfigurable fault-tolerant VLSI arrays using the Diogenes methodology. The authors compare their designs to those in the literature and are shown to be superior with respect to I/O format, control, and delay from input to output.

Research Organization:
Dept. of Electrical Engineering-Systems, Univ. of Southern California, Los Angeles, CA (US)
OSTI ID:
6243175
Journal Information:
IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 38:3; ISSN ITCOB
Country of Publication:
United States
Language:
English

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