Designing linear systolic arrays
- University of Southern California, Los Angeles, CA (USA). Dept. of Electrical Engineering
The authors develop a simple mapping technique to design linear systolic arrays. The basic idea of the technique is to map the computations of a certain class of two-dimensional systolic arrays onto one-dimensional arrays. Using this technique, systolic algorithms are derived for problems such as matrix multiplication and transitive closure on linearly connected arrays of PEs with constant I/O bandwidth. Compared to known designs in the literature, the technique leads to modular systolic arrays with constant hardware in each PE, few control lines, lexicographic data input/output, and improved delay time. The unidirectional flow of control and data in this design assures implementation of the linear array in the known fault models of wafer scale integration.
- OSTI ID:
- 6960988
- Journal Information:
- Journal of Parallel and Distributed Computing; (USA), Journal Name: Journal of Parallel and Distributed Computing; (USA) Vol. 7:3; ISSN JPDCE; ISSN 0743-7315
- Country of Publication:
- United States
- Language:
- English
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