Highly vectorizable fault simulation on the Cray X-MP supercomputer

Journal Article · Fri Dec 01 04:00:00 EST 1989 · IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems; (USA)

DOI:https://doi.org/10.1109/43.44516· OSTI ID:6987691

Daoud, R; Ozguner, F ^[1]

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1. Dept. of Electrical Engineering, Ohio State Univ., Columbus, OH (USA)

A highly vectorizable parallel fault simulation (HVPFS) algorithm for high-speed fault simulation of combinational circuits, developed to take advantage of the specific hardware architecture of the Cray X-MP vector supercomputer is described. The algorithm takes into account the memory organization of the supercomputer, reduces the number of vector fetches per gate simulation, and overlaps computation and I/O. Experimental results on large benchmark circuits show that very high evaluation rates (3 {minus} 3.5 {times} 10{sup 9} evaluations/s.) comparable to those of hardware logic simulation engines can be achieved. Speedup factors of 50-60 are observed between scalar and vector execution of the simulator on the Cray X-MP/28.

• OSTI ID: 6987691
• Journal Information: IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems; (USA), Journal Name: IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems; (USA) Vol. 8:12; ISSN ITCSD; ISSN 0278-0070
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
BENCHMARKS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
COMPUTERS
CRAY COMPUTERS
PARALLEL PROCESSING
PROGRAMMING
SIMULATION
VECTOR PROCESSING