Design and analysis of fault-tolerant processor arrays for numerical applications
Thesis/Dissertation
·
OSTI ID:6963943
The availability of fast devices in low-cost and high-density technologies promises a major breakthrough in future supercomputer designs, especially in the design of highly concurrent processors. Locally inter-connected processor arrays, such as systolic arrays, are well suited to efficiently implement a major class of numerical algorithms due to their massive parallelism and regular structure. However, the successful operation of a processor array depends very much on the correctness of all the processing elements in the array. In the first part of this thesis, a fault-tolerance scheme using an encoding based on the linear property is proposed; this can be applied to a class of processor arrays where each processor in the regular part of the array is a linear system. Many algorithms in digital signal processing and matrix operations are shown to be mapped to systems which belong to this class. In the next section, a novel concurrent error-detection technique using residue codes is proposed, which can be applied to the processor arrays derived from signal flow graphs. After detecting an error, fault location is performed either through some special algorithms or though the use of time redundancy.
- Research Organization:
- Illinois Univ., Urbana (USA)
- OSTI ID:
- 6963943
- Country of Publication:
- United States
- Language:
- English
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