Iterative improvement in the design of a restricted class of VLSI macrocells

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:6961201

Konechny, Jr, E T

This dissertation demonstrates new techniques for the design of VLSI elemental circuit cell entities. At the elementary circuit level, the desired objective is formulated based solely on device description equations and is minimized locally to an initial circuit design. For the system-level, the design improvement of the complete VLSI macro-digital circuit is accomplished in a hierarchical fashion. The desired objective function is cast in terms of gross variables based on the partially ordered structure of objective functions for elemental circuit entities composing the macrocell. As examples, the objective of power delay was minimized for NMOS inverter and S-R-flip-flop circuits. The objective of total propagation delay was minimized for a shift-register macrocell and was compared to the individual flip-flop circuit results. A sequence of constrained linear programming (LP) solution steps, guided by a specific convergence parameter, was used to find the minimum performance objective in each of these examples. The algorithm is computer-time-efficient and can be used interactively by a VLSI circuit designer.

• Research Organization: George Washington Univ., Washington, DC (USA)
• OSTI ID: 6961201
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990220 -- Computers
Computerized Models
& Computer Programs-- (1987-1989)
ALGORITHMS
COMPUTER-AIDED DESIGN
DIGITAL CIRCUITS
ELECTRONIC CIRCUITS
FLIP-FLOP CIRCUITS
INTEGRATED CIRCUITS
LINEAR PROGRAMMING
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
MULTIVIBRATORS
PROGRAMMING
PULSE CIRCUITS
SEMICONDUCTOR DEVICES
TRANSISTORS