Planar tungsten interconnect
A method of forming an interconnect level for VLSI devices is described comprising: forming on planar surface of a VLSI wafer a first silicon dioxide dielectric layer; forming a second layer of a second dielectric material on the top surface of the first layer to produce a composite dielectric; patterning and etching the composite dielectric to produce at least one interconnect channel in the first layer; implanting silicon in the exposed bottom surface of the silicon dioxide interconnect channel through the mask; removing the mask; selectively depositing a refractionary metal in the interconnect channel to fill the channel to the level of the planar top surface of the first layer to thereby form a metal interconnect line, the line and the first layer forming a first planar interconnect level.
- Assignee:
- Cornell Research Foundation, Inc., Ithaca, NY
- Patent Number(s):
- US 4746621
- OSTI ID:
- 6955781
- Country of Publication:
- United States
- Language:
- English
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Planarization of metal films for multilevel interconnects
Planarization of metal films for multilevel interconnects
Related Subjects
360104 -- Metals & Alloys-- Physical Properties
42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
ALLOYS
CHALCOGENIDES
DIELECTRIC MATERIALS
ELECTRICAL PROPERTIES
ELECTRONIC CIRCUITS
ELEMENTS
FABRICATION
INTEGRATED CIRCUITS
JUNCTIONS
LAYERS
MATERIALS
METALS
MICROELECTRONIC CIRCUITS
OXIDES
OXYGEN COMPOUNDS
PHYSICAL PROPERTIES
REFRACTORY METALS
SILICON COMPOUNDS
SILICON OXIDES
TRANSITION ELEMENTS
TUNGSTEN