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SEU characterization of a hardened CMOS 64K and 256K SRAM

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)
DOI:https://doi.org/10.1109/23.45441· OSTI ID:6907792
;  [1];  [2];  [3]
  1. Sandia National Lab., Albuquerque, NM (US)
  2. AT and T Bell Lab., Allentown, PA (US)
  3. Aerospace Corp., Los Angeles, CA (US)

This paper reports on single-event-upset (SEU) tests of the AT and T 64K and 256K SRAMs. Feedback resistor values for these parts ranged from 200k{Omega} to 1M{Omega}. All were fabricated using the 1-{mu}m 2-level poly, 2-level metal process. Ions used for these tests were Ar, Cu, Kr, and Xe providing a range of effective LET values from 20 to 129 MeV-cm{sup 2}/mg. With the 64K SRAM operating at 4.5 volts and 90{degrees}C, and upset threshold LET of 30 MeV-cm{sup 2}/mg and saturation cross-section of 1.5 {times} 10{sup {minus} 2} cm{sup 2} were measured with a nominal room temperature feedback resistance of 450k{Omega}. In Adam's 10% worst-case environment using the Petersen approximation, this implies an error rate of 1.3 {times} 10{sup {minus} 7} errors per bit-day. With a nominal 650k{Omega} feedback resistance, a 256K SRAM had a calculated error rate of about 3 {times} 10{sup {minus} 8} errors per bit-day at 4.5 volts and 90{degrees}C. This data agree well with earlier data for a 1K-bit test chip. The minimal feedback resistance required to prevent upset vs. LET is calculated by assuming an activation energy of 0.10 eV to estimate the decrease in feedback resistor value as a function of temperature.

DOE Contract Number:
AC04-76DP00789
OSTI ID:
6907792
Report Number(s):
CONF-890723--
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA) Vol. 36:6; ISSN 0018-9499; ISSN IETNA
Country of Publication:
United States
Language:
English