SEU simulation and testing of resistor-hardened D-latches in the SA3300 microprocessor

Conference · Sun Dec 01 04:00:00 EST 1991 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)

DOI:https://doi.org/10.1109/23.124141· OSTI ID:5613797

Sexton, F W; Corbett, W T; Treece, R K; Hass, K J; Axness, C L; Hash, G L; Shaneyfelt, M R; Wunsch, T F ^[1]; Hughes, K L ^[2]

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1. Sandia National Labs., Albuquerque, NM (United States)
2. L and M Associates, Albuquerque, NM (US)

In this paper the SEU tolerance of the SA3300 microprocessor with feedback resistors is presented and compared to the SA3300 without feedback resistors and to the commercial version (NS32016). Upset threshold at room temperature increased from 23 MeV-cm{sup 2}/mg and 180 MeV-cm{sup 2}/mg with feedback resistors of 50 k{Omega} and 160 k{Omega}, respectively. The performance goal of 10 MHz over the full temperature range of {minus}55{degrees} C to +125{degrees} C is exceeded for feedback resistors of 160 k{Omega} and less. Error rate calculations for this design predict that the error rate is less than once every 100 years when 50 k{Omega} feedback resistors are used in the D-latch design. Analysis of the SEU response using a lumped-parameter circuit simulator imply a charge collection depth of 4.5 {mu}m. This is much deeper than the authors would expect for prompt collection in the epi and funnel regions and has been explained in terms of diffusion current in the heavily doped substrate.

• DOE Contract Number: AC04-76DP00789
• OSTI ID: 5613797
• Report Number(s): CONF-910751--
• Conference Information: Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Journal Volume: 38:6
• Country of Publication: United States
• Language: English

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