Serendipitous SEU hardening of resistive load SRAMs
Journal Article
·
· IEEE Transactions on Nuclear Science
- Aerospace Corp., Los Angeles, CA (United States)
High and low resistive load versions of Micron Technology`s MT5C1008C (128K {times} 8) and MT5C2561C (256K {times} 1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a 1 {r_arrow} 0 to 0 {r_arrow} 1 bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.
- OSTI ID:
- 277734
- Report Number(s):
- CONF-9509107--
- Journal Information:
- IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 3Pt1 Vol. 43; ISSN IETNAE; ISSN 0018-9499
- Country of Publication:
- United States
- Language:
- English
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