Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, 64K x 1 NMOS SRAMs
Long time constants associated with extremely high pull-up resistances commonly used in high-density, poly-silicon load NMOS SRAMs have been identified as the primary cause of single-event-induced, multiple bit upsets recently observed in cyclotron tests. Diffusion currents can cause single event errors in this long time constant regime. Above certain threshold LETs, multiple bit upsets constitute almost the entirety of single event errors in these SRAMs. Conventionally calculated error cross-sections can be larger than the chip area and may result in unreasonably large bit error rates. A new method of defining the SEU figure-of-merit in space environments which includes multiple bit upsets is thus urgently needed.
- Research Organization:
- TRW Inc., Redondo Beach, CA (US); The Aerospace Corp., Los Angeles, CA (US); UCLA, Los Angeles, CA (US)
- OSTI ID:
- 6166300
- Report Number(s):
- CONF-880730-
- Journal Information:
- IEEE Trans. Nucl. Sci.; (United States), Journal Name: IEEE Trans. Nucl. Sci.; (United States) Vol. 35:6; ISSN IETNA
- Country of Publication:
- United States
- Language:
- English
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73 NUCLEAR PHYSICS AND RADIATION PHYSICS
ACCELERATORS
ANALYTICAL SOLUTION
CHARGED-PARTICLE TRANSPORT
CURRENTS
CYCLIC ACCELERATORS
CYCLOTRONS
DATA
DIFFUSION
ELECTRIC CURRENTS
ELEMENTS
ENERGY TRANSFER
ENVIRONMENT
ERRORS
EXPERIMENTAL DATA
INFORMATION
LEAKAGE CURRENT
LET
MEMORY DEVICES
MOS TRANSISTORS
NUMERICAL DATA
PERFORMANCE
RADIATION EFFECTS
RADIATION TRANSPORT
SEMICONDUCTOR DEVICES
SEMIMETALS
SILICON
SPACE FLIGHT
TRANSISTORS