Dead-time free pixel readout architecture for ATLAS front-end IC

Journal Article · Tue Jun 01 04:00:00 EDT 1999 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.775508· OSTI ID:679549

Einsweiler, K; Joshi, A; Kleinfelder, S; Luo, L; Marchesini, R; Milgrome, O; Pengg, F ^[1]

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1. Lawrence Berkeley National Lab., CA (United States)

A low-power, sparse-scan, readout architecture has been developed for the ATLAS pixel front-end electronics. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address of the hits and associates them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 {micro} HP process to meet the requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC has been found to provide dead-time-less ambiguity-free readout at 40 MHz data rate.

• OSTI ID: 679549
• Report Number(s): CONF-981110--
• Journal Information: IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 3Pt1 Vol. 46; ISSN IETNAE; ISSN 0018-9499
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
CERN LHC
DEAD TIME
DESIGN
DISCRIMINATORS
INTEGRATED CIRCUITS
RADIATION DETECTORS
READOUT SYSTEMS