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The FE-I4 Pixel Readout Chip and the IBL Module

Journal Article · · PoS Vertex2011:038,2011
OSTI ID:1039544
FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.
Research Organization:
SLAC National Accelerator Laboratory (SLAC)
Sponsoring Organization:
DOE; US DOE Office of Science (DOE SC)
DOE Contract Number:
AC02-76SF00515
OSTI ID:
1039544
Report Number(s):
SLAC-PUB-14958
Journal Information:
PoS Vertex2011:038,2011, Journal Name: PoS Vertex2011:038,2011
Country of Publication:
United States
Language:
English

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