Hierarchical gate-array routing on a hypercube multiprocessor

Journal Article · Sun Apr 01 04:00:00 EDT 1990 · Journal of Parallel and Distributed Computing; (USA)

DOI:https://doi.org/10.1016/0743-7315(90)90130-H· OSTI ID:6779338

Olukotun, O A; Mudge, T N ^[1]

---

1. Dept. of Electrical Engineering and Computer Science, Univ. of Michigan, Ann Arbor, MI (US)

Gate-arrays are the most common design style for semicustom VLSI integrated circuits. An important part of the gate-array design process is the routing of wires between the logic elements, which is an extremely compute-intensive operation. This paper presents an algorithm for routing gate-arrays that uses a hypercube connected parallel processor to provide the necessary computation power. In order to make optimal use of the hypercube, the routing algorithm is organized do that inter-processor communication is kept to a minimum. It occurs only during the global routing and crossing placement phases of the algorithm, which constitute less than 15% of the total running time of the algorithm. On the basis of the results of executing the algorithm on two gate-array benchmarks the case is made for using hypercube multiprocessors as accelerators for compute-intensive CAD operations.

• OSTI ID: 6779338
• Journal Information: Journal of Parallel and Distributed Computing; (USA), Journal Name: Journal of Parallel and Distributed Computing; (USA) Vol. 8:4; ISSN JPDCE; ISSN 0743-7315
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
BENCHMARKS
COMMUNICATIONS
COMPUTERS
DESIGN
ELECTRONIC CIRCUITS
GATING CIRCUITS
HYPERCUBE COMPUTERS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PROGRAMMING