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Novel circuits for radiation hardened memories

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)
OSTI ID:6712972
;  [1];  [2];  [3]
  1. Microcirc Associates, Newport Beach, CA (United States)
  2. Hughes Aircraft (United States)
  3. AMI-Gould (United States)

This paper reports on implementation of large storage semiconductor memories which combine radiation hardness with high packing density, operational speed, and low power dissipation and require both hardened circuit and hardened process technologies. Novel circuits, including orthogonal shuffle type of write-read arrays, error correction by weighted bidirectional codes and associative iterative repair circuits, are proposed for significant improvements of SRAMs' immunity against the effects of total dose and cosmic particle impacts. The implementation of the proposed circuit resulted in fault-tolerant 40-Mbit and 10-Mbit monolithic memories featuring a data rate of 120 MHz and power dissipation of 880 mW. These experimental serial-parallel memories were fabricated with a nonhardened standard CMOS processing technology, yet provided a total dose hardness of 1 Mrad and a projected SEU rate of 1 [times] 10[sup [minus] 12] error/bit/day. Using radiation hardened processing improvements by factors of 10 to 100 are predicted in both total dose hardness and SEU rate.

OSTI ID:
6712972
Report Number(s):
CONF-911106--
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Vol. 39:5; ISSN 0018-9499; ISSN IETNAE
Country of Publication:
United States
Language:
English