SEU-hardened resistive-load static RAMs

Conference · Sat Nov 30 23:00:00 EST 1991 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)

OSTI ID:5707977

Massengill, L W ^[1]

---

1. Vanderbilt Univ., Nashville, TN (United States). Dept. of Electrical Engineering

In this paper a charge partitioning (CP) design technique for MOS resistive-load static RAMs (RMOS SRAMs) is presented. This technique, when applied to RMOS SRAMs with specific capacitance attributes, may produce significant SEU error-rate control without sacrifices in area or power consumption. Silicon-on-insulator (SOI) technology, usually not considered appropriate for conventional RMOS SRAMs because of reduced storage capacitances, appears to be an excellent technology for CP-hardened RMOS. Simulated CP-hardened, 4-transistor RMOS RAM cells in SOI approach the error-rate performance of rad-hard, full 6-transistor CMOS cells.

• OSTI ID: 5707977
• Report Number(s): CONF-910751--
• Journal Information: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Vol. 38:6; ISSN 0018-9499; ISSN IETNA
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
440200* -- Radiation Effects on Instrument Components
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
CAPACITANCE
CONTROL
DESIGN
ELECTRIC CHARGES
ELECTRICAL EQUIPMENT
ELECTRICAL PROPERTIES
ELEMENTS
EQUIPMENT
ERRORS
HARDENING
MOS TRANSISTORS
PERFORMANCE
PHYSICAL PROPERTIES
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATION HARDENING
RESISTORS
SEMICONDUCTOR DEVICES
SEMIMETALS
SILICON
SIMULATION
TRANSISTORS