Access ordering and coherence in shared-memory multi-processors
Shared memory forms a convenient communication medium in a multitasking multiprocessor system. However, different multiprocessors can execute the same program in different manners, possibly yielding incorrect results because the machines adhere to different rules. Differences in behavior are due to the varying approaches of designers to attack the shared memory access latency problem in multiprocessors. In particular, the manner in which multiple copies of data are controlled and the manner in which memory accesses are sequenced, propagated, and buffered has impact on the behavior of the multiprocessor. Three shared memory execution models, referred to as concurrency models, are defined. The precise properties of processors, memories, and interconnection networks are derived to comply to each of the concurrency models. The usefulness of these concurrency models is demonstrated by showing the simplicity with which their rules can be applied to allow buffering of memory accesses, implement combining networks, prove cache coherence protocols correct, and design lockup-free caches. Specific examples are provided, both of a cache-based multiprocessor potentially without bottlenecks and of a cache-based multiprocessor employing lockup-free caches which can continue to service the processor while concurrently servicing one of several access misses. The paradigms and associated conditions presented in this thesis form a set of powerful tools allowing multiprocessor designers to concentrate on functionality while being burdened less with side-effect analysis.
- Research Organization:
- University of Southern California, Los Angeles, CA (USA)
- OSTI ID:
- 6596355
- Country of Publication:
- United States
- Language:
- English
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