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Memory access dependencies in shared-memory multiprocessors

Journal Article · · IEEE (Institute of Electrical and Electronics Engineers) Transactions on Software Engineering; (USA)
DOI:https://doi.org/10.1109/32.55094· OSTI ID:6411036
;  [1]
  1. Dept. of Electrical Engineering-Systems, Univ. of Southern California, Los Angeles, CA (US)

A multiprocessor system designed to support multithreading must adhere to a simple logical model of concurrency. Besides executing each process correctly, the multiprocessor must preserve the dependencies among processes. Dependencies among concurrent processes are specified by explicit statements such as critical sections or by the sharing of writable data. Parallelizing compilers and programmers using concurrent languages must conform to the model of concurrency of the machine, to generate correct code. The presence of high-performance mechanisms in shared-memory multiprocessors, such as private caches, extensive pipelining of memory accesses and combining networks may render a logical concurrency model complex to implement or inefficient. In this paper, the problem of implementing a given logical concurrency model of multi-processor is addressed.

OSTI ID:
6411036
Journal Information:
IEEE (Institute of Electrical and Electronics Engineers) Transactions on Software Engineering; (USA), Journal Name: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Software Engineering; (USA) Vol. 16:6; ISSN 0098-5589; ISSN IESED
Country of Publication:
United States
Language:
English