Cache-coherence problem in shared-memory multiprocessors
Shared-memory multiprocessors offer increased computational power and the programmability of the shared-memory model. However, sharing memory between processors leads to contention that delays memory accesses. Adding a cache memory for each processor reduces the average access time, but it creates the possibility of inconsistency among cached copies. The cache coherence problem is keeping all cached copies of the same memory location identical. This dissertation explores possible solutions to the cache-coherence problem and identifies cache-coherence protocols - solutions implemented entirely in hardware - as an attractive alternative. Protocols for shared-bus systems are shown to be an interesting special case. Previously proposed shared-bus protocols are described using uniform terminology, and they are shown to divide into two categories; invalidation and distributed write. In each category, a new protocol is presented with better performance than previous schemes, based on simulation results. The simulation model and parameters are described in detail. Previous protocols for general interconnection networks are shown to contain flaws and to be costly to implement and a new class of protocols is presented. Previous definitions of cache coherence are shown to be inadequate and a new definition is presented.
- Research Organization:
- Washington Univ., Seattle (USA)
- OSTI ID:
- 5152229
- Country of Publication:
- United States
- Language:
- English
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