Analysis of multiple-bus interconnection networks

Journal Article · Mon Sep 01 04:00:00 EDT 1986 · J. Parallel Distrib. Comput.; (United States)

DOI:https://doi.org/10.1016/0743-7315(86)90019-5· OSTI ID:6576207

Mudge, T N; Hayes, J P; Buzzard, G D; Winsor, D C

The performance of multiple-bus interconnection networks for multiprocessor systems is analyzed, taking into account conflict arising from memory and bus interference. A discrete stochastic model of bandwidth is presented for systems in which each memory is connected either to all the buses or to a subset of the available buses. The effects of the assumptions made concerning independence among requests for different memories (spatial independence) and resubmission of blocked requests (temporal independence) are investigated systematically. The basic bandwidth model is extended to account for spatial dependence, and compared to previously proposed models. Finally, the various analytic models are shown to be in close agreement with simulation results.

• Research Organization: Advanced Computer Architecture Lab., Dept. of Electrical Engineering and Computer Science, Univ. of Michigan, Ann Arbor, MI 48109-1109
• OSTI ID: 6576207
• Journal Information: J. Parallel Distrib. Comput.; (United States), Journal Name: J. Parallel Distrib. Comput.; (United States) Vol. 3:3; ISSN JPDCE
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
BAND THEORY
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
COMPUTERS
DATA TRANSMISSION SYSTEMS
DIGITAL COMPUTERS
EQUIPMENT INTERFACES
MATHEMATICAL MODELS
MEMORY DEVICES
PERFORMANCE
SIMULATION
SPACE DEPENDENCE
STOCHASTIC PROCESSES
SUPERCOMPUTERS