Multiple bus architectures

Journal Article · Mon Jun 01 04:00:00 EDT 1987 · Computer; (United States)

DOI:https://doi.org/10.1109/MC.1987.1663590· OSTI ID:5686816

Mudge, T N; Hayes, J P; Winsor, D C ^[1]

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1. Univ. of Michigan, Ann Arbor, MI

A recent study noted that for shared memory multiprocessors the single system bus typically used to connect the processor to the memory is by far the most limiting resource, and system performance can be increased considerably by increasing the capacity of the bus. One way of increasing the bus capacity, and also the system's reliability and fault tolerance, is to increase the number of buses. In this article the authors discuss using multiple buses to provide highbandwidth connections between the processors and the shared memory, thereby allowing the construction of larger and more powerful systems than currently possible.

• OSTI ID: 5686816
• Journal Information: Computer; (United States), Journal Name: Computer; (United States) Vol. 20:6; ISSN 0018-9162; ISSN CPTRB
• Country of Publication: United States
• Language: ENGLISH

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
BAND THEORY
COMPUTER ARCHITECTURE
CONSTRUCTION
DATA TRANSMISSION
DATA TRANSMISSION SYSTEMS
EQUIPMENT INTERFACES
MEMORY DEVICES
PERFORMANCE
SUPERCOMPUTERS