Wafer-scale integration and two-level pipelined implementations of systolic arrays

Journal Article · Wed Aug 01 04:00:00 EDT 1984 · J. Parallel Distrib. Comput.; (United States)

DOI:https://doi.org/10.1016/0743-7315(84)90010-8· OSTI ID:6574383

Kung, H T; Lam, M S

For problems that have been solved exclusively by systolic arrays with feedback cycles, this paper introduces a new class of systolic algorithms based on a ring architecture. These systolic rings have the property that the throughput degrades gracefully as the number of failed cells in the rings increases. Furthermore, as a byproduct of the ring architecture approach, the authors have derived several new systolic algorithms which require only one-third to one-half of the cells used in previous designs while achieving the same throughput. They have shown that the two-level pipelining problem in systolic arrays are solved by the same techniques used to solve the fault-tolerance problem. An important task left for the future is the development of software to solve both problems automatically.

• Research Organization: Dept. of Computer Science, Carnegie-Mellon Univ., Pittsburgh, PA 15213
• OSTI ID: 6574383
• Journal Information: J. Parallel Distrib. Comput.; (United States), Journal Name: J. Parallel Distrib. Comput.; (United States) Vol. 1:1; ISSN JPDCE
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERS
DATA TRANSMISSION
DATA-FLOW PROCESSING
DESIGN
DIGITAL COMPUTERS
FAULT TOLERANT COMPUTERS
FEEDBACK
MATHEMATICAL MODELS
MEMORY DEVICES
PERFORMANCE
PROGRAMMING
RELIABILITY
TIME DEPENDENCE