Nanosequencer digital logic controller
This patent describes a logic controller receiving status line inputs with status states thereof defining conditional instructions to the logic controller and having a single memory access time to access an instruction having a fixed duration instruction execution time. The controller consists of: a memory means having address lines for storing instructions and providing first output lines, the memory having segments associated with the status of the plurality of status line inputs and having stored therein instructions for application to the first output lines with each instruction including separate bit sequences for controlling logic control, status select, and next address lines; register means connected to and supplied by the first output lines for receiving an instruction from the memory means and providing the instruction on a second output lines, the output lines including logic control, status select, and next address lines for respectively emitting the bit sequences received from the memory means thereat; means connecting the next address lines of the second output lines from the register means to the address lines of the memory means; status control selection means connected to receive status line inputs and connected to and controlled by the status select lines of the second output lines for selection, once each instruction execution time, one status line input from among the status line inputs based upon the bit sequence emitted by the register means at the status select lines.
- Assignee:
- US National Aeronautics and Space Administration, Washington, DC
- Patent Number(s):
- US 4766533
- OSTI ID:
- 6525350
- Country of Publication:
- United States
- Language:
- English
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