Analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process
The use of a p/sup +/ buried layer beneath the p-well in CMOS is evaluated for controlling latch-up (parasitic SCR action). It is shown that this structure typically reduces the parasitic npn transistor's current gain by two orders of magnitude. The npn gain reduction is the principal mechanism for latch-up control. The npn has been studied using STRAP to numerically solve the transport equations. These simulations show the npn current gain to be primarily governed by the base-retarding field arising from the impurity gradient of the outdiffusing buried layer. A new wide-base lateral pnp model has been developed to accurately model the field enhancement of the parasitic lateral pnp's current gain. Experimental confirmation of the lateral pnp model is given.
- Research Organization:
- Sandia Labs., Albuquerque, NM (USA); Stanford Univ., Palo Alto, CA (USA)
- DOE Contract Number:
- EY-76-C-04-0789
- OSTI ID:
- 6482359
- Report Number(s):
- SAND-78-1648C; CONF-781210-2
- Country of Publication:
- United States
- Language:
- English
Similar Records
Neutron-induced latch-up immunity in metal gate CMOS integrated circuits
Latch-up control in CMOS integrated circuits
Related Subjects
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ELECTRONIC CIRCUITS
FABRICATION
HARDENING
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
PERFORMANCE
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATION HARDENING
SEMICONDUCTOR DEVICES
TRANSISTORS