Latch-up control in CMOS integrated circuits

Conference · Mon Jan 01 04:00:00 EST 1979

OSTI ID:6099727

Ochoa, A Jr; Estreich, D B; Dawes, Jr, W R

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed.

• Research Organization: Sandia Labs., Albuquerque, NM (USA)
• DOE Contract Number: EY-76-C-04-0789
• OSTI ID: 6099727
• Report Number(s): SAND-79-0646C; CONF-790706-1
• Country of Publication: United States
• Language: English

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46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ELECTRONIC CIRCUITS
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INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
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