Latch-up control in CMOS integrated circuits

Conference · Fri Jul 13 04:00:00 UTC 1979

OSTI ID:5547811

Ochoa, A; Dawes, W; Estreich, D; Packard, H

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 ..mu..m p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 ..mu..m p-well) CMOS and indicates the extent of their applicability to VLSI designs.

• Research Organization: Sandia Labs., Albuquerque, NM (USA)
• DOE Contract Number: EY-76-C-04-0789
• OSTI ID: 5547811
• Report Number(s): SAND-79-1479C; CONF-790706-7
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS