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Latch-up CMOS/EPI devices

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)
OSTI ID:5767754
 [1];  [2];  [3]
  1. Centre National d'Etudes Spatiales, 18 Av. Edouard Belin, 31055 Toulouse Cedex (FR)
  2. Z.I. Flourens, 31130 Balma (FR)
  3. Inst. de Physique Nucleaire, BP 1-91406, Orsay Cedex (FR)

New space projects tend to use more and more VLSI circuits manufactured in CMOS technology. Assessment of latch-up sensitivity is mandatory in the evaluation plan of a component, and in some cases the result could be considered as a GO/NOGO parameter. The authors present data on several CMOS/EPI devices demonstrating the non-efficiency of an epitaxial layer to achieve latch-up immunity for some latest technologies.

OSTI ID:
5767754
Report Number(s):
CONF-900723--
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA) Vol. 37:6; ISSN 0018-9499; ISSN IETNA
Country of Publication:
United States
Language:
English