Prevention of CMOS latch-up by gold doping

Conference · Wed Dec 31 23:00:00 EST 1975

OSTI ID:7343198

Dawes, W R; Derbenwick, G F

CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices.

• Research Organization: Sandia Labs., Albuquerque, N.Mex. (USA)
• DOE Contract Number: AT(29-1)-789
• OSTI ID: 7343198
• Report Number(s): SAND-76-5296; CONF-760728-3
• Country of Publication: United States
• Language: English

Related Subjects

440200* -- Radiation Effects on Instrument Components
Instruments
or Electronic Systems
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
CRYSTAL DOPING
ELECTRONIC CIRCUITS
ELEMENTS
FABRICATION
FAILURES
GOLD
HARDENING
INTEGRATED CIRCUITS
METALS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
OVERVOLTAGE
PHYSICAL RADIATION EFFECTS
RADIATION EFFECTS
RADIATION HARDENING
SEMICONDUCTOR DEVICES
SEMIMETALS
SILICON
TRANSISTORS
TRANSITION ELEMENTS