A multiple floating point coprocessor architecture
- Center for Supercomputing Research and Development, Univ. of Illinois at Urbana-Champaign, 305 Talbot Lab., Urbana, IL (US)
General purpose microprocessor based computers usually speed their arithmetic processing performance by using a floating point co-processor. Because adding more co-processors represents neither a technological nor a cost problem the authors investigated a system based on a MIPS R2000 (2) and 4 floating point units. In this paper they show a block diagram of such an implementation and how two important scientific operations can be accelerated using a single unmodified data bus. A large percentage of the engineering applications are solved with the help of linear algebra methods like BLAS3 (4) algorithms; it is precisely for these primitives that the proposed architecture brings significant performance gains. The first operation described is a matrix multiplication algorithm, its timing diagram and some results. Next a polynomial evaluation technique is examined. The authors show how to use the same ideas with various other microprocessors.
- OSTI ID:
- 6476390
- Journal Information:
- Computer Architecture News; (USA), Journal Name: Computer Architecture News; (USA) Vol. 18:2; ISSN CANED; ISSN 0163-5964
- Country of Publication:
- United States
- Language:
- English
Similar Records
Software implementation of floating-Point arithmetic on a reduced-Instruction-set processor
Floating-point standards: Theory and practice