Method of fabricating semiconductor device having low resistance non-alloyed contact layer

Patent · Tue May 05 00:00:00 EDT 1987

OSTI ID:6416585

Aina, O A; Lakhani, A A

A method is described of fabricating a semiconductor device in a compound substrate, comprising the steps of: forming an active region in the substrate; forming a gate electrode in a selected portion of the active region; and forming source and drain electrodes by depositing on the source and drain contact layers, respectively, an electrode material selected from the group comprising gold, tungsten, gold-titanium alloys and gold-germanium-nickel alloys. The barrier height across the interfaces of the source and drain electrodes and the non-alloyed contact layer is lower than the barrier height across an interface of the source and drain electrodes and the active region.

• Assignee: Allied Corp., Morristown, NJ
• Patent Number(s): US 4662060
• OSTI ID: 6416585
• Resource Relation: Patent File Date: Filed date 13 Dec 1985
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
36 MATERIALS SCIENCE
GERMANIUM ALLOYS
ELECTRODEPOSITION
ION IMPLANTATION
GOLD ALLOYS
NICKEL ALLOYS
SEMICONDUCTOR DEVICES
FABRICATION
MATERIALS
TITANIUM ALLOYS
CHEMICAL COMPOSITION
ELECTRODES
INTERFACES
LAYERS
SUBSTRATES
ALLOYS
DEPOSITION
ELECTROLYSIS
LYSIS
SURFACE COATING
420800* - Engineering- Electronic Circuits & Devices- (-1989)
360106 - Metals & Alloys- Radiation Effects