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Feasibility of an ultra-high-speed Josephson multiplier

Journal Article · · IEEE J. Solid-State Circuits; (United States)
In this paper, the authors discuss the design, fabrication, and evaluation of a Josephson multiplier model featuring all niobium junctions. They designed a 16-bit X 16-bit parallel multiplier and fabricated its critical path model consisting of 828 gates. The circuit was designed using modified variable threshold logic (MVTL) or gates and single-junction AND gates. These gates consisted of Nb/AlO/sub x//Nb Josephson junctions, Nb wirings, Mo resistors, and SiO/sub 2/ insulators. Both the minimum linewidth and junction diameter were 2.5 ..mu..m. The observed multiplication time using the critical path model was 1.1 ns. The propagation delay due to the interconnecting wirings was estimated to be 0.20 ns, and the longest path of the circuit consisted of 103 gates. Thus the average gate delay in the circuit was estimated to be 8.7 ps/gate. These results point to the possibility of an ultra-high-speed multiplier, about five times faster than any other semiconductor device.
Research Organization:
Fujitsu Ltd., 10-1, Morinosato-Wakamiya, Atsugi-shi 243-01
OSTI ID:
6411398
Journal Information:
IEEE J. Solid-State Circuits; (United States), Journal Name: IEEE J. Solid-State Circuits; (United States) Vol. SC-22:1; ISSN IJSCB
Country of Publication:
United States
Language:
English