Josephson modified variable threshold logic gates for use in ultra-high-speed LSI

Journal Article · Wed Feb 01 04:00:00 EST 1989 · IEEE Trans. Electron Devices; (United States)

DOI:https://doi.org/10.1109/16.19947· OSTI ID:5774624

Fujimaki, N; Kotani, S; Imamura, T; Hasuo, S

There are two important questions concerning the design and construction of Josephson large-scale integrated circuits: what is the best logic gate and how is the gate powered Surveying the published performance of the various Josephson logic gates, the authors obtained the following design principles. The gate delay and the dissipated power depend mainly on the current level and not on the gate structure. To decrease the gate area, inductors with many magnetically coupled control lines are not preferred. However, inductors with only one magnetically coupled control line have a smaller area than the gate electrode, and can be used. The authors propose a gate family called Modified Variable Threshold Logic (MVTL) based on these principles. The OR gate is a two-junction interferometer with one magnetically coupled control line. Magnetic coupling and current injection are used to switch the logic state of the gate. By optimizing the gate parameters, they obtained an operating margin of +-43 percent and a switching speed of 2.5 ps/gate. The gate area was 30 /mu/m x 24 /mu/m with a 1.5-/mu/m minimum junction diameter. The gate family consists of an OR gate, a single-junction AND gate, and a timed inverter (TI) that consists of the OR gate, a junction, and resistors. The delay time of the gate operated in the actual circuit was found to be less than 10 ps. Circuits having up to 1000 gates, the critical path model of a 16-bit x 16-bit multiplier and 16-bit arithmetic logic unit (ALU) have been successfully operated. When the Josephson gate is operated with three-phase power, we can construct any sequential circuit without the complex latch circuit required to prevent the race condition for one- or two-phase power supplied.

• Research Organization: Fujitsu Ltd., 10-1 Morinosato-Wakamiya, Atsugi, 243-01 (JP)
• OSTI ID: 5774624
• Journal Information: IEEE Trans. Electron Devices; (United States), Journal Name: IEEE Trans. Electron Devices; (United States) Vol. 36:2; ISSN IETDA
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420201* -- Engineering-- Cryogenic Equipment & Devices
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
COUPLING
DESIGN
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
LOGIC CIRCUITS
MICROELECTRONIC CIRCUITS
MODIFICATIONS
OPTIMIZATION
PARAMETRIC ANALYSIS
PERFORMANCE
SUPERCONDUCTING JUNCTIONS