Distributed computer architecture for real-time, data driven applications
A distributed, fault-tolerant, highly reconfigurable macro level pipeline computer architecture which is readily adaptable to a real-time data flow environment is described. The architecture consists of a number of loosely coupled computing elements (CEs) which may be linked to data and file memories through fully nonblocking interconnect networks. Data is moved through the architecture by the routing of control tokens from CE to CE. Because the control tokens are requests for processes and not requests for physical destinations, the architecture is a true virtual processor design at the CE level. The architecture exhibits two levels of reconfigurability-system-level and CE-level. An operating system for the architecture is presented at a functional level. It is fault-tolerant, portions of it are implemented in hardware, and the software portion resides in a subset of the CEs. 24 references.
- OSTI ID:
- 6281958
- Country of Publication:
- United States
- Language:
- English
Similar Records
Fault tolerance in parallel architectures. Final report, June 1982-December 1985
Algorithm implementation and design of reconfigurable mixed systolic arrays