Electronic systems miniaturization using programmable logic devices

Technical Report · Mon Oct 01 04:00:00 EDT 1990

DOI:https://doi.org/10.2172/6278105· OSTI ID:6278105

Ashton, E C; Bergeson, G C

This report describes the steps which were taken to miniaturize a target circuit using Erasable Programmable Logic Devices (EPLDs). The original objective of this project was to explore the miniaturization of a circuit using both Application Specific Integrated Circuits (ASICs) and EPLDs to meet the following goals: balance cost and circuit density; reduce fabrication time; improve quality control issues by keeping much of the design in-house; and eliminate security risks by partitioning the design into ASIC and PLD (EPLD) sections. Due to cost considerations, the target circuit was miniaturized using only PLDs. The results of this project indicate that PLDs are capable of realizing fairly dense circuitry, are considerably less expensive than ASICs (by a factor of 500--1000), and are able to eliminate security risks and reduce fabrication time by keeping the design completely in-house.

• Research Organization: EG and G Idaho, Inc., Idaho Falls, ID (USA)
• Sponsoring Organization: DOE/DP
• DOE Contract Number: AC07-76ID01570
• OSTI ID: 6278105
• Report Number(s): EGG-EE-9258; ON: DE91006214
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200 -- Mathematics & Computers
COMPUTER ARCHITECTURE
CONTROL
COST
DESIGN
DIAGRAMS
ELECTRONIC CIRCUITS
ELECTRONIC EQUIPMENT
ENGINEERING DRAWINGS
EQUIPMENT
FABRICATION
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MICROELECTRONIC CIRCUITS
MINIATURIZATION
MULTIPLEXERS
QUALITY CONTROL
SECURITY