Motorola MC68040 high-speed design using Altera EPM5000 Erasable programmable logic devices
Conference
·
OSTI ID:10178522
Many designs use EPLD`s (Erasable Programmable Logic Devices) to implement control logic and state machines. If the design is slow, timing through the EPLD is not crucial so designers often treat the device as a black box. In high speed designs, timing through the EPLD is critical. In these cases a thorough understanding of the device architecture is necessary. This paper discusses lessons learned in the implementation of a high-speed design using the Altera EPM5130.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 10178522
- Report Number(s):
- SAND--93-1598C; CONF-9309201--1; ON: DE93017635
- Country of Publication:
- United States
- Language:
- English
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