Thin-film chip-to-substrate interconnect and methods for making same
Integrated circuit chips are electrically connected to a silicon wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability. 6 figs.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- DOE Contract Number:
- W-7405-ENG-48
- Assignee:
- Dept. of Energy
- Patent Number(s):
- PATENTS-US-A7202296
- Application Number:
- ON: DE89009657
- OSTI ID:
- 6277342
- Resource Relation:
- Other Information: Portions of this document are illegible in microfiche products
- Country of Publication:
- United States
- Language:
- English
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