Instruction issuing mechanism for processors with multiple functional units
An instruction issuing system for a processor is described including an execution unit having multiple functional units comprising: an instruction issuing unit receiving instructions from a memory, operating on instructions and forwarding instructions to the execution unit, the instruction issuing unit including means for detecting the existence of concurrencies in the instructions received from the memory; and the instruction issuing unit further including means for issuing multiple instructions and non-sequential instructions to the execution unit within a single processor cycle when a concurrency is detected by the means for detecting the existence of concurrencies in the instructions.
- Assignee:
- Cornell Research Foundation, Inc., Ithaca, NY
- Patent Number(s):
- US 4807115
- OSTI ID:
- 6243157
- Country of Publication:
- United States
- Language:
- English
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