An instruction issuing approach to enhancing performance in multiple functional unit processors

Journal Article · Mon Sep 01 00:00:00 EDT 1986 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1986.1676841· OSTI ID:5271341

Acosta, R D; Kjelstrup, J; Torng, H C

Processors with multiple functional units, such as CRAY-1, Cyber 205, and FPS 164, have been used for high-end scientific computation tasks. Much effort has been put into increasing the throughput of such systems. One critical consideration in their design is the identification and implementation of a suitable instruction issuing scheme. Existing approaches do not issue enough instructions per machine cycle to fully utilize the functional units and realize the high-performance level achievable with these powerful execution resources. In this paper, the dispatch stack (DS), an innovative instruction issuing approach designed to overcome this limitation, is presented. The DS enhances performance in these systems by employing dynamic code scheduling to permit 1) one or more instructions to be issued per machine cycle and 2) instructions to be issued nonsequentially. The effectiveness of the DS has been evaluated with extensive simulation using the Livermore Loops. The simulation results, which cover various Instruction/Execution unit configurations, are presented here. The statistics obtained establish that instruction issuing with DS results in speedups ranging from 1.71 to 2.79 over serial dispatching schemes.

• Research Organization: Microelectronics and Computer Technology Corp., Austin, TX 78759
• OSTI ID: 5271341
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-35:9; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
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DATA PROCESSING
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MATHEMATICAL LOGIC
MATHEMATICS
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