Embedded conductors by electrochemical planarization

Conference · Fri Mar 31 23:00:00 EST 1989

OSTI ID:6237668

Contolini, R. J.; Bernhardt, A. F.; Tuckerman, D. B.

An electrochemical process is described for planarization of metal interconnect layers on integrated circuits and multichip modules. Electroplating is used to deposit metal over a patterned SiO/sub 2/ dielectric, followed by electropolishing to remove excess metal. Electropolishing simultaneously smooths and further flattens the surface. The process yields a planar surface with conductors embedded in the etched regions of the dielectric. It is shown that pulsed plating is superior to galvanostatic plating in this application. 12 refs., 6 figs.

• Research Organization: Lawrence Livermore National Lab., CA (USA)
• DOE Contract Number: W-7405-ENG-48
• OSTI ID: 6237668
• Report Number(s): UCRL-100692; CONF-890518-2; ON: DE89011632
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
360601* -- Other Materials-- Preparation & Manufacture
CHALCOGENIDES
CHEMICAL COATING
CHEMICAL VAPOR DEPOSITION
CHROMIUM
COPPER
DEPOSITION
ELECTRIC CONDUCTORS
ELECTRODEPOSITION
ELECTROLYSIS
ELECTRONIC CIRCUITS
ELECTROPLATING
ELECTROPOLISHING
ELEMENTS
ETCHING
INTEGRATED CIRCUITS
LYSIS
METALS
MICROELECTRONIC CIRCUITS
OXIDES
OXYGEN COMPOUNDS
PLATING
POLISHING
SILICON COMPOUNDS
SILICON OXIDES
SURFACE COATING
SURFACE FINISHING
TITANIUM
TRANSITION ELEMENTS