Electrochemical planarization for multilevel metallization

Journal Article · Thu Sep 01 00:00:00 EDT 1994 · Journal of the Electrochemical Society; (United States)

DOI:https://doi.org/10.1149/1.2055151· OSTI ID:6955509

Contolini, R J; Bernhardt, A F; Mayer, S T ^[1]

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1. Lawrence Livermore National Lab., Livermore, CA (United States)

The authors describe an electrochemical planarization technology involving electroplating followed by electropolishing, resulting in a very flat surface containing embedded conductors. Electrochemical planarization technology has been used to produce silicon substrate multichip modules. Both the electroplating and electropolishing processes have a thickness uniformity of better than [+-] 2% ([+-]3[sigma]) across a 100 mm wafer.

• DOE Contract Number: W-7405-ENG-48
• OSTI ID: 6955509
• Journal Information: Journal of the Electrochemical Society; (United States), Journal Name: Journal of the Electrochemical Society; (United States) Vol. 141:9; ISSN JESOAN; ISSN 0013-4651
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
360601* -- Other Materials-- Preparation & Manufacture
42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
COATINGS
COPPER
DEPOSITION
ELECTRODEPOSITED COATINGS
ELECTRODEPOSITION
ELECTROLYSIS
ELECTRONIC CIRCUITS
ELECTROPLATING
ELECTROPOLISHING
ELEMENTS
ETCHING
FABRICATION
INTEGRATED CIRCUITS
LYSIS
METALS
MICROELECTRONIC CIRCUITS
PLATING
POLISHING
SEMIMETALS
SILICON
SURFACE COATING
SURFACE FINISHING
TRANSITION ELEMENTS