Concurrent-error detection and correction algorithm for fault-tolerant VLSI arithmetic array processors

Thesis/Dissertation · Tue Jan 01 00:00:00 EST 1985

OSTI ID:6138028

Shokoohi-Kayvan, K

A concurrent-error detection and correction algorithm for errors caused by permanent, intermittent and transient faults in arithmetic parallel-pipeline array processors, is described. The fault model, applicable to VLSI implementations, assumes the occurrence of faults with unknown origin and frequency. Recovery from faults is achieved through minimal processing element (PE) redundancy in the array architecture, facilitated by spatial bypassing of the correct operands previous to the occurrence of a fault to fault-free PE's and recomputing during the following clock cycles. The overhead hardware and timing are determined. It is shown that this concurrent-error detection and correction techniques uses less additional hardware than RESO (REcomputing with Shifted Operands), offers marginal timing improvement over the RESO technique, and adds the concurrent error correction capability which is not present in RESO. Furthermore, the additional hardware and control for error detection and recovery is local and modular, hence making this technique very attractive for VLSI implementations.

• Research Organization: Michigan State Univ., East Lansing (USA)
• OSTI ID: 6138028
• Resource Relation: Other Information: Thesis (Ph. D.)
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
FAULT TOLERANT COMPUTERS
ERRORS
COMPUTER ARCHITECTURE
CORRECTIONS
DETECTION
INTEGRATED CIRCUITS
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
MICROELECTRONIC CIRCUITS
990210* - Supercomputers- (1987-1989)