Fault tolerant matrix arithmetic and signal processing on highly concurrent VLSI systems
In the first part of this research, a very general matrix encoding scheme is proposed for achieving fault tolerance with low cost in matrix arithmetic and signal processing systems using linear arrays and fixed point number representation. Such arrays are believed to hold the most promise in VLSI computing structures for their flexibility, low cost, and applicability to many interesting algorithms. In floating point systems, roundoff errors may destroy the error correction capability of this encoding scheme. However, the encoding scheme combined with a data retry technique is shown to be useful and cost-effective for floating point systems. The Fast Fourier Transform (FFT) has long been a major analytical tool in such diverse fields as system analysis, digital filtering, power spectrum analysis, and communication theory. In this second part of this research, a concurrent error detection (CED) scheme with small hardware overhead is proposed for FFT networks that consist of (N/2-log/sub 2/N 2-point butterfly modules. A time redundancy method is used to locate the faulty modules. Finally multiplexer-demultiplexer type of switches incorporated in the design are used to effect reconfiguration.
- Research Organization:
- Illinois Univ., Urbana (USA)
- OSTI ID:
- 5520122
- Country of Publication:
- United States
- Language:
- English
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