Apparatus for packing parallel data words having a variable width into parallel data words having a fixed width
This patent describes an apparatus for packing data, receiving parallel data words having a width equal to a variable number of n valid data bits, and providing parallel output data works having a width equal to a fixed number of m valid data bits. It comprises a control circuit for receiving a signal corresponding to a binary representation of the number n for each received data word, the signal having a most significant bit (MSB) portion when n is equal to or greater than m, and a least significant bit (LSB) portion, corresponding to least significant bits of the number n, the MSB portion being applied by the control circuit as a first MSB control signal, the control circuit comprising an adder means; the adder means receiving and summing subsequently received LSB portions of the signal to provide a running sum, and for providing a second MSB control signal corresponding to an MSB portion of the running sum when the running sum is equal to or greater than m, the adder means further providing a third control signal corresponding to an LSB portion of the running sum; bits shifter means for receiving the third control signal, receiving and shifting the parallel data words by a number of bit positions corresponding to the third control signal; and data output means for receiving and storing data bits from the bit shifter means in a received order, and for providing an m-bit wide packed parallel output word at an occurrence of one of the first and second MSB control signal.
- Assignee:
- Ampex Corp., Redwood City, CA (USA)
- Patent Number(s):
- US 4963867; A
- Application Number:
- PPN: US 7-331977
- OSTI ID:
- 6098076
- Country of Publication:
- United States
- Language:
- English
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