A fabrication process for a 580ps 4 Kbit Josephson non-destructive read-out RAM

Conference · Fri Mar 01 04:00:00 EST 1991 · IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States)

OSTI ID:6090158

Ishida, I; Tahara, S; Hidaka, M; Nagasawa, S; Tsuchida, S; Wada, Y ^[1]

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1. NEC Corp., Fundamental Research Lab., 34 Miyukigaoka, Tsukuba, Ibaraki (JP)

This paper reports on the development of a 4 Kbit Josephson non-destructive read-out (NDRO) random access memory (RAM). A process for fabricating the 580 ps 4 Kbit Josephson NDRO RAM is described that is based primarily on the use of Nb/AlOx/Nb technology and state-of-the-art planarization. The process has evolved from 1 Kbit Josephson NDRO RAM previously reported, with changes having occurred in a memory cell structure, a multilevel construction, layer planarization and minimum design rules. Advanced memory cells having 2 stacked superconducting, layer planarization and minimum design rules. Advanced memory cells having 2 stacked superconducting loops on which control lines are prepared are formed on ground plane insulation layers.

• OSTI ID: 6090158
• Report Number(s): CONF-900944--
• Conference Information: Journal Name: IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States) Journal Volume: 27:2
• Country of Publication: United States
• Language: English

Related Subjects

665412* -- Superconducting Devices-- (1992-)
75 CONDENSED MATTER PHYSICS
SUPERCONDUCTIVITY AND SUPERFLUIDITY
ALUMINIUM COMPOUNDS
ALUMINIUM OXIDES
CHALCOGENIDES
DOMAIN STRUCTURE
ELECTRIC CONDUCTIVITY
ELECTRICAL EQUIPMENT
ELECTRICAL PROPERTIES
ELEMENTS
EQUIPMENT
FABRICATION
JOSEPHSON JUNCTIONS
JUNCTIONS
LAYERS
MEMORY MANAGEMENT
METALS
NIOBIUM
OXIDES
OXYGEN COMPOUNDS
PHYSICAL PROPERTIES
RESISTORS
SILICON COMPOUNDS
SILICON OXIDES
SUPERCONDUCTING DEVICES
SUPERCONDUCTING JUNCTIONS
SUPERCONDUCTIVITY
TECHNOLOGY UTILIZATION
TRANSITION ELEMENTS