4-kbit Josephson nondestructive read-out RAM operated at 580 psec and 6. 7 MW
- Fundamental Research Lab., NEC Corp., 34 Miyukigaoka, Tsukuba, Ibaraki 305 (JP)
This paper proposes a fully decoded 4-kbit Josephson non-destructive read-out high-speed RAM with vortex transitional memory cells designed and operated successfully. The 4-kbit Josephson RAM is composed of 64 {times} 64 bit cells, polarity-convertible drivers, address decoders using resistor coupled Josephson logic (RCJL) gates and a resistively loaded sense circuit. The memory cells employ vortex transitions in their superconducting loops for writing and reading data. The cells are activated by two control signals without timing control, while all peripheral circuits are activated by an AC power supply. This memory configuration eliminates the timing sequence needed for memory operations, resulting in a decrease in the memory operation time for an actual memory chip. The 4-kbit Josephson high-speed RAM is fabricated using niobium planarization technique with a 1.5-{mu}m design rule. The RAM circuit size is 4.8 {times} 4.8 mm{sup 2} and the memory cell is 55 {times} 55 {mu}m{sup 2}.
- OSTI ID:
- 5690166
- Report Number(s):
- CONF-900944--
- Journal Information:
- IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States) Vol. 27:2; ISSN IEMGA; ISSN 0018-9464
- Country of Publication:
- United States
- Language:
- English
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