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An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

Journal Article · · IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)
; ; ; ;  [1];  [2]; ;  [3]
  1. Central Research Lab., Hitachi Ltd., Kokubunji, Tokyo (JP)
  2. Hitachi Device Engineering Co. Ltd., Mobara, Chiba (JP)
  3. Device Development Center, Hitachi, Ltd., Ohme, Tokyo (JP)

An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune switched-load-resistor memory cell with clamp transistors, an upward-transistor decoder utilizing a sidewall-base contact structure (SICOS) upward transistor for the AND gate, a Darlington word driver with advanced discharge circuits, and 0.8 {mu}m SICOS technology. High-load and low-load resistors in this new memory cell are formed by suing double-layer polysilicon for the base and emitter electrodes in the SICOS structure. This results in a small cell size (498 {mu}m{sup 2}) and a reasonable chip size (85.8 mm{sup 2}). An accelerated soft-error test using americium alpha source shows that the new 64-kbit RAM has sufficient soft-error immunity, in spite of its small cell capacitance which is about one third that of conventional RAM's. In addition to the new memory cell, the upward-transistor decoder and the Darlington word driver with advanced discharge circuits make it possible to realize a high-speed, large-capacity bipolar RAM, while maintaining soft-error immunity.

OSTI ID:
6924000
Journal Information:
IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA) Vol. 24:5; ISSN IJSCB; ISSN 0018-9200
Country of Publication:
United States
Language:
English

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