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Processing techniques for refractory integrated circuits

Conference · · IEEE Trans. Magn.; (United States)
OSTI ID:6086811
Processing techniques have been developed to increase yields and uniformity in superconductor integrated circuits labricated with refractory materials. An eight level process was used to define a ground plane, ground plane insulator, Josephson junction base and counter electrodes, a second insulator layer, superconductor interconnections, resistors, and gold contact pads. Every layer, except the gold, was patterned by reactive ion etching. A new resistor structure was developed that included an etch stop layer. The formation of polymers, which occurs with etch gases containing carbon, was inhibited by the addition of oxygen to the plasma. Reactive ion etching of insulator vias was accomplished with a mixture of NF/sub 3/ and Ar that gave good selectivity for silicon dioxide over niobium. Stress-free films of niobium, molybdenum, and silicon dioxide were obtained by adjusting the sputtering gas pressure. Molybdenum resistors, deposited as a top layer, were trimmed by RIE as a post-testing step to improve circuit performance.
Research Organization:
Westinghouse R and D Center, Pittsburgh, PA (US); Intermagnetics General Corp., Guilderland, NY (US)
OSTI ID:
6086811
Report Number(s):
CONF-880812-
Conference Information:
Journal Name: IEEE Trans. Magn.; (United States) Journal Volume: 25:2
Country of Publication:
United States
Language:
English