Piecewise data flow architecture control flow and register management
Journal Article
·
· IEEE Computer Society reprint; (United States)
The hardware register management and instruction block control flow sequencing provided by the PDF block processing section of the Piecewise Data Flow machine, a proposed high performance computer architecture, is presented. Combined, these capabilities provide the maximum allowed execution overlap of instruction blocks with minimum hardware contention and high hardware utilization.
- Research Organization:
- Lawrence Livermore National Lab., CA
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 6083796
- Journal Information:
- IEEE Computer Society reprint; (United States), Journal Name: IEEE Computer Society reprint; (United States)
- Country of Publication:
- United States
- Language:
- English
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