Piecewise data flow architecture: architectural concepts

Journal Article · Sun May 01 04:00:00 EDT 1983 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1983.1676253· OSTI ID:5436851

Requa, J E; Mcgraw, J R

This paper presents the design and a brief analysis of the piecewise data flow computer (PDF), an architecture proposed for very high-performance computing. PDE is a heterogeneous multiprocessor system having both SIMD and MIMD characteristics. Each computation is translated into a control flow graph in which each node contains a basic block of instructions. Concurrency can be exploited in three different ways: simultaneous execution of independent basic blocks, simultaneous execution of independent instructions within a basic block, and intrinsic array operations. This program representation is amenable to traditional languages (e.g., FORTRAN) because almost all optimizing compilers use basic blocks as their internal representation. New functional languages should be able to exploit this architecture even more easily. The most significant aspects of the PDF architecture concern scheduling basic blocks for execution, allocating registers to intermediate results, and assigning instructions to processors. 22 references.

• Research Organization: Lawrence Livermore National Lab., CA
• OSTI ID: 5436851
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 5; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARCHITECTURE
ARRAY PROCESSORS
COMPUTERS
DATA-FLOW PROCESSING
DIGITAL COMPUTERS
PARALLEL PROCESSING
PROGRAMMING
SUPERCOMPUTERS