Strategies for managing the register file in RISC

Journal Article · Tue Nov 01 04:00:00 EST 1983 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1983.1676149· OSTI ID:5363768

Tamir, Y; Sequin, C H

The RISC (reduced instruction-set computer) architecture attempts to achieve high performance without resorting to complex instructions and irregular pipelining schemes. One of the novel features of this architecure is a large register file which is used to minimize the overhead involved in procedure calls and returns. The authors investigate several strategies for managing this register file. The costs of practical strategies are compared with a lower bound on this management overhead, obtained from a theoretical optimal strategy, for several register file sizes. While the results concern specifically the RISC processor recently built at the University of California at Berkeley, they are generally applicable to other processors with multiple register banks. 11 references.

• Research Organization: Univ. of California, Berkeley
• OSTI ID: 5363768
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 11; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARCHITECTURE
COMPUTERS
PERFORMANCE